CACHE COHERENCE VS CONSISTENCY SOFTWARE
CACHE COHERENCE VS CONSISTENCY CODE
CACHE COHERENCE VS CONSISTENCY SERIES

The below examples basically shows where memory order really matters. Memory consistency determines the possible memory orders for a sequence of memory accesses ( CPU pipeline operates on smaller granularity than cache line size, besides, we don’t have semantic such as transaction to enforce atoimc). Here, we show some real world examples to demonstrate the importance of memory consistency. The above snippet is kind of unrealistic. However, this requires both programming model and hardware changes to support. This is what transactional memory offers. If we borrow atomicity concept from database field, we can gracefully solve the concurrency problem (memory ordering or memory consistency, synchronization, etc.). As I mentioned earlier, consistency model mainly deal the concurrent programming model. In memory system, the database operations can be replaced with memory operations (e.g.

CACHE COHERENCE VS CONSISTENCY SERIES

Since the hardware (cache system) support 64B granularity coherence, does it mean we can guarantee 16B memory to be coherent? AtomicityĪtomicity is an important database concept which defines indivisible and irreducible series of database operations such that either all occurs, or nothing occurs. This actually leads to the next concept we want to talk about which is atomicity.

CACHE COHERENCE VS CONSISTENCY SOFTWARE

However, in software point of view, we see coherence in load/store granularity (1B/2B/4B/8B) since generally we don’t deal with load/store on more than 8B size. For example, for cache coherency, we only care about cache line size (64B). Consistency deals with the ordering of operations to multiple locations with respect to all processors.īasically, coherence usually deal with the smallest granularity of read and write to memory system. However, the core difference between coherence and consistency is as quote in Wiki, Coherence deals with maintaining a global order in which writes to a single location or single variable are seen by all processors. Or it can be a distributed system which has multiple cached copies on different nodes with the same storage backend. As the other post I wrote for cache coherence, the shared memory system can be a modern multi-core chip which has local L1/L2 caches for each core.

CoherenceĬoherence is also used to define behavior of read and write to a shared memory system. More details will be elaborated in the following sections. In modern architectures (x86, arm), the answer is yes, 00 is possible.

CACHE COHERENCE VS CONSISTENCY CODE

However, can the code print out 00? (It seems impossible since it contradict to sequential program order.) Well, that’s what memory consistency model defines. Due to the parallelism of different cores, it’s obvious the above code can print out different results based on execution order ( 10 - (1)(2)(3)(4), 11 - (1)(3)(2)(4)). The inline assembly ensures compiler not reorder (1) and (2) although they are not dependent. Most programmer understand that compiler may reorder instructions to improve efficiency. The above table demonstrates an example of memory consistency. (init) A = 0 B = 0Īsm volatile(“”:::”memory) // Prevent compiler reorder By specifying a consistency model, programmers will be guaranteed to obtain predicted results after reading, writing, or updating memory. ConsistencyĬonsistency or consistency model mainly specifies a contract between programmer and system on concurrent programming model. Before diving in the main topic of this post which is memory consistency and memory order, I’ll clarify some related concept and motivate the topic.

Cache coherence vs consistency